Electronic products have been developed to have low profile, multiple functions and high and rapid performance, making printed circuit board (PCB) or integrated circuit (IC) packaging substrate formed with fine circuits and small pitches. Current PCB or IC packaging substrate has dimensions including line width, trace pitch and aspect ratio reduced from greater than 100 μm to about 30 μm, and further dimensional decrease is endeavored. Therefore, how to fabricate a circuit board with fine circuits arranged in high density and fine vias, which can reduce the number of laminated layers in a substrate but not significantly increase the fabrication cost, is an important topic sought to be achieved in the IC and other related electronic industries. The circuit build-up technology plays a key role in determining the density of circuits during fabrication of the circuit board, such that a pattern plating method or SAP (semi-addition process) technique is commonly employed to form fine build-up circuits for the circuit board.
FIGS. 1A to 1D show procedural steps for the conventional pattern plating method. Referring to FIG. 1A, a core circuit board 11 is prepared. An insulating layer 12 with a metal conductive layer 121, such as resin coated with copper (RCC), is formed respectively on upper and lower surfaces of the core circuit board 11, and a plurality of holes 120 are formed in the insulating layer 12 by laser drilling to expose predetermined parts of the inner circuits 110.
Referring to FIG. 1B, a conductive seed layer 13 (such as electroless-plated copper layer) is formed on the metal conductive layer 121 and the exposed parts of the inner circuits 110. A resist layer 14 is applied over the seed layer 13 and formed with a plurality of holes for exposing predetermined parts of the seed layer 13. Then a patterned circuit layer 15 is deposited by electroplating on the exposed parts of the seed layer 13. Alternatively for the SAP technique, a conductive seed layer is directly formed on the insulating layer on each of the surfaces of the core circuit board, and other fabrication processes are similar to the pattern plating method, thereby not further to be repeated here.
Referring to FIG. 1C, the resist layer 14 is removed. The seed layer 13 and the metal conductive layer 121, which are originally covered by the resist layer 14, are etched away. Then the above fabrication processes are repeated to form more insulating layers and build-up circuit layers so as to form a multi-layer circuit board.
The circuit layer 15 on the surface of the circuit board partly extends to form electrical connection pads for transmission of electrical signals or power. Metal layer such as Ni (nickel)/Au (gold) is usually formed on an exposed surface of each of the electrical connection pads to facilitate bonding between the electrical connection pads and conductive elements such as gold wires, solder bumps, pre-solder bumps or solder balls that are electrically coupled to a chip or circuit board. Further, the metal layer helps prevent the electrical connection pads from oxidation if they are exposed.
The seed layer 13 and the metal conductive layer 121 for the electrical conduction purpose are etched away and removed after the patterned circuit layer 15 is electroplated. For protecting the circuit layer 15 on the surface of the circuit board against external contamination, a solder mask 16 such as green paint is applied on the circuit layer 15 by printing or coating, and is patterned to form a plurality of openings 160 to expose the electrical connection pads of the circuit layer 15. Subsequently, an electroless plating process such as electroless nickel/immersion gold (EN/IG) is performed to deposit a Ni/Au metal layer 17 on each of the electrical connection pads exposed via the openings 160, as shown in FIG. 1D.
On the other hand, an electroplating process may also be employed to form the Ni/Au metal layer on the electrical connection pads of the circuit layer 15. However, the seed layer 13 and the metal conductive layer 121, serving as electrical conductive paths, are made of copper that is the same material forming the circuit layer 15. After completing the electroplating process, the etching process for removing the seed layer 13 and the metal conductive layer 121 underneath the resist layer 14 would also cause the circuit layer 15 to be etched and damaged, leading to deformation or shrinkage of the circuit layer 15. Compared to the SAP technique, this problem is more severe in the pattern plating method, because the extra metal conductive layer 121 on the insulating layer 12 requires much time in process for etching away, thereby making the circuit layer 15 more seriously damaged and deformed e.g. shrinkage. The damage and shrinkage would adversely affect the electrical performance of the circuit board especially formed with fine and densely arranged circuits.
Moreover, for miniaturizing the size and increasing the functions of electronic products, the circuits are becoming more densely arranged in the circuit board, and thus the laminated layers of the circuit board are becoming thinner. In such a case, copper particles forming the circuits may migrate and diffuse to the insulating layer, causing the copper migration effect in the insulating layer between adjacent circuits or adjacent circuit layers. Also in the densely packed circuit board, the insulating layer is sized relatively thinner. As a result, if the thinner insulating layer contains conductive copper particles, the insulation effect would be degraded and easily result in short circuit between adjacent circuits or adjacent circuit layers, making the circuit board fail. Further, with the usage time of the circuit board increased, the copper migration effect becomes more serious that more and more copper particles would move to the insulating layer, making the insulating layer become conductive and lose its insulation property.
Therefore, the problem to be solved herein is to provide a substrate or circuit board with densely arranged circuits and build-up layers, which can avoid the copper migration effect and prevent the circuits from being damaged or deformed (e.g. shrinkage) by etching.